Switch Bounce Tutorials

Switch Bounce

Microcontrolers may not in Human thinking frequency .Human thinking frequency is lies in some of low Hz .  Microcontroler works variety range of frequency ie ,12Mhz,20 Mhz etc .  In a push Button  micro controller interfacing, Human and Micro controller are feels that whether the push is pressed or not  in different way as follows in the graph .

Some small duration pulse due to denounce generated as multiple touch error
Hardware solution

It can be made by a resistor and a capacitor in the following manner or any other for comfortable

When ever the switch is pressed the capacitor will charge  rapidly ,practically the first charge wil be across  the  ,capacitor ,

So we can avoid the denouncing effect .

The capacitor and the resistor will be select in accordance with time constant . as follows

For more information go here

Will be update 

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Switch Bounce Tutorials

Switch Bounce

Microcontrolers may not in Human thinking frequency .Human thinking frequency is lies in some of low Hz .  Microcontroler works variety range of frequency ie ,12Mhz,20 Mhz etc .  In a push Button  micro controller interfacing, Human and Micro controller are feels that whether the push is pressed or not  in different way as follows in the graph .

Some small duration pulse due to denounce generated as multiple touch error
Hardware solution

It can be made by a resistor and a capacitor in the following manner or any other for comfortable

When ever the switch is pressed the capacitor will charge  rapidly ,practically the first charge wil be across  the  ,capacitor ,

So we can avoid the denouncing effect .

The capacitor and the resistor will be select in accordance with time constant . as follows

For more information go here

Will be update 

Read More

Design of Digital Voltmeter By using Micro-controller Part 2

 Microcontroller based Digital AC Meter Part 2 Code And Circuit

First Part available here

Circuit Diagram 

#include"lcd.h"
#include "adc.h"
#include "delay.h"
double volt_read_disply();
int main(void)
  
{   
     int adc_value1=0;  
  LCD_SetUp(PB_0,PB_1,PB_2,P_NC,P_NC,P_NC,P_NC,PB_4,PB_5,PB_6,PB_7);
  LCD_Init(2,16);     
     adc_init();
    
     LCD_Clear();
  LCD_GoToXY(0,0);  
  
  LCD_DisplayString("  g-Electron"); 
  _delay_ms(1000); 
  
 while(1) 
 {  
       adc_value1 =  volt_read_disply();
    LCD_GoToLine(1);  
    LCD_DisplayString(" Volt : ");    
    LCD_DisplayNumber(10,adc_value1,3);   
    LCD_DisplayString("V");  
    _delay_ms(1300);
 } 
}

double volt_read_disply()
{   int i,adc_value[40]={0}; int temp =0;
 
 adc_init();

  for(i=0; i<40;i++)                        // samples taking from 41 times 9.4milli second taken about on complte half cycle
   { 
   adc_value[i] = read_adc(0);  // reading voltage           
  }
   
  temp = adc_value[0];  
 for(i=0; i<40; i++)
 {
  if(temp<adc_value[i])
  temp=adc_value[i];
 }  
 
      return ((double)temp*0.224828935); // int to double casting
   
}

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Design of Digital Voltmeter By using Micro-controller Part 2

 Microcontroller based Digital AC Meter Part 2 Code And Circuit

First Part available here

Circuit Diagram 

#include"lcd.h"
#include "adc.h"
#include "delay.h"
double volt_read_disply();
int main(void)
  
{   
     int adc_value1=0;  
  LCD_SetUp(PB_0,PB_1,PB_2,P_NC,P_NC,P_NC,P_NC,PB_4,PB_5,PB_6,PB_7);
  LCD_Init(2,16);     
     adc_init();
    
     LCD_Clear();
  LCD_GoToXY(0,0);  
  
  LCD_DisplayString("  g-Electron"); 
  _delay_ms(1000); 
  
 while(1) 
 {  
       adc_value1 =  volt_read_disply();
    LCD_GoToLine(1);  
    LCD_DisplayString(" Volt : ");    
    LCD_DisplayNumber(10,adc_value1,3);   
    LCD_DisplayString("V");  
    _delay_ms(1300);
 } 
}

double volt_read_disply()
{   int i,adc_value[40]={0}; int temp =0;
 
 adc_init();

  for(i=0; i<40;i++)                        // samples taking from 41 times 9.4milli second taken about on complte half cycle
   { 
   adc_value[i] = read_adc(0);  // reading voltage           
  }
   
  temp = adc_value[0];  
 for(i=0; i<40; i++)
 {
  if(temp<adc_value[i])
  temp=adc_value[i];
 }  
 
      return ((double)temp*0.224828935); // int to double casting
   
}

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Transformer Configuration in Proteus

Setting up A Transformer in Proteus

The calculation Formula is  L1/L2 = (V1/V2)^2

For Example: Design for 6 Volt input ,230volt 50Hz Not considered wattage just for simulation. 

           Assign L1 = 1H (but 1henry expectable for a 10 or 20 kW transformer)

        Then L2 = 1/(230/6)^2

                       = 680.5293micro Henry

more

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Transformer Configuration in Proteus

Setting up A Transformer in Proteus

The calculation Formula is  L1/L2 = (V1/V2)^2

For Example: Design for 6 Volt input ,230volt 50Hz Not considered wattage just for simulation. 

           Assign L1 = 1H (but 1henry expectable for a 10 or 20 kW transformer)

        Then L2 = 1/(230/6)^2

                       = 680.5293micro Henry

more

Read More

Design of Digital Voltmeter By using Microcontroller

Tutorial for Atmeag8 /AVR based Voltmeter

               It measures the Ac voltage and shows readings in RMS value.

Basics Of AC signal 

The AC signal ,its amplitude varying in accordance with time. In india AC frequency is 50Hz.

Then the Time period one full cycle ,

        

  T = 1/frequency 

  T = 1/50Hz = .002second 

                     = 20milli Second

                     = 10 Milli second for Half Cycle

There are a lot of methods for measuring AC volt digitally

we could find the RMS value by multipliying the Peak Voltage with 0.707. 

   Vrms = Peak Voltage * 0.707 .

Approximatly Indian Line AC Peak volatge is 325v.

  Example : 

                 325v *0.707 = 229.775Volt      .(appro = 230Vrms).

But Microcontroller could only sense  up to 5 volt  as well as it couldnt sense negative values

so we cannot  give 230 volt directly to It .

It can be rectify by using a Stepdown transformer ,which has an advantage of safety.

Ac voltage can be reduce by using transformer to comfortable range . (ie 0 to 5volt DC)

make the calculation  as   ,

 The voltage Divider would give a 5 volt when the Vrms 230v. [will be more give details on the way ].

The full wave rectifier output will give to ADC of micro controller . Then do corresponding coding.

Microcontroller Section 

I am using here Amega8. 

we need to mesure only one half cycles repeatedly because  the waves same are repeating 

Basics

I selected , the F_cpu frequency is the internal RC Oscillator 8MHz.

Atmega8 ADC uses Prescalar [frequency reducer or divider by 2th,4th etc]

Atmega ADC  Prescale Frequency is in between 50Khz to 200Kz

ADC conversion time is in between 13 to 260 micro second.

ADC frequency = F_cpu / Prescaler

                         = 800,000HZ  / 8

  

                        = 62.5KHz

At high frequency ADC conversion would be fast while at lower frequency the conversion will be more accuracy.

ADC conversion time Calculation 

Conversion Time = 1/ADC frequency

                           = 1/62500 

                           = 0.000016 Second

                           = 0.016 Milli Second

                           = 16 Micro Second.     [At 62.500KHz]

So 16 mirco second would taken for one cycle of  conversion.with 62,5KHz.

13 ADC cycles required for one conversion

ie,

    13 * 16Micro Second = 230 Micro Second [approximately]

                                      = 230us.

The Half wave has 10milli second time duration.[100000microsecond].

There the available conversion times is 

                                        =  Total time period for a half cycle /one ADC conversion time  

                                        

                                        = 10000 micro second / 230 micro second

                 

                                        = 43.4 samples  [ for one half cycleie 10 milli second]

                                       

    Image Shows only 7 Samples per half cycles .in our case it is 43

And again reduced the sampling to 40 .

calculation of Vpeak

 Takes the largest Vpeak from the 40 samples.

Vrms = Vpeak * .707

*****************************************************************************

Atmega8 ADC StepSize Calculation

Atmega8 uses successive approximation adc  ,

The Atmega8 ADC is a 10 Bit /[ie the Maximum high value is 1023 =1111111111] at which the ADC will give fullscale Value .

The ADC  require a clock as well as a reference voltage .

The resolution of ADC output decide the Step size.

ADC o/p = Vin * 1024 / Vref

Examples;

  Vin =5volt , Vref =5volt 

                 ADC o/p = 5 * 1023 /5 = 1023 [ADC highest Value]

               Step Size  voltage = Vref / 1023 = 0.004887 volt =4.88millivolt

             One binary digit changes when 4.88volt changes takes place

           

     

Image's Step Size is 1.25 volt

*******************************************************************************************************

Go Here for Part 2 

Read More

Design of Digital Voltmeter By using Microcontroller

Tutorial for Atmeag8 /AVR based Voltmeter

               It measures the Ac voltage and shows readings in RMS value.

Basics Of AC signal 

The AC signal ,its amplitude varying in accordance with time. In india AC frequency is 50Hz.

Then the Time period one full cycle ,

        

  T = 1/frequency 

  T = 1/50Hz = .002second 

                     = 20milli Second

                     = 10 Milli second for Half Cycle

There are a lot of methods for measuring AC volt digitally

we could find the RMS value by multipliying the Peak Voltage with 0.707. 

   Vrms = Peak Voltage * 0.707 .

Approximatly Indian Line AC Peak volatge is 325v.

  Example : 

                 325v *0.707 = 229.775Volt      .(appro = 230Vrms).

But Microcontroller could only sense  up to 5 volt  as well as it couldnt sense negative values

so we cannot  give 230 volt directly to It .

It can be rectify by using a Stepdown transformer ,which has an advantage of safety.

Ac voltage can be reduce by using transformer to comfortable range . (ie 0 to 5volt DC)

make the calculation  as   ,

 The voltage Divider would give a 5 volt when the Vrms 230v. [will be more give details on the way ].

The full wave rectifier output will give to ADC of micro controller . Then do corresponding coding.

Microcontroller Section 

I am using here Amega8. 

we need to mesure only one half cycles repeatedly because  the waves same are repeating 

Basics

I selected , the F_cpu frequency is the internal RC Oscillator 8MHz.

Atmega8 ADC uses Prescalar [frequency reducer or divider by 2th,4th etc]

Atmega ADC  Prescale Frequency is in between 50Khz to 200Kz

ADC conversion time is in between 13 to 260 micro second.

ADC frequency = F_cpu / Prescaler

                         = 800,000HZ  / 8

  

                        = 62.5KHz

At high frequency ADC conversion would be fast while at lower frequency the conversion will be more accuracy.

ADC conversion time Calculation 

Conversion Time = 1/ADC frequency

                           = 1/62500 

                           = 0.000016 Second

                           = 0.016 Milli Second

                           = 16 Micro Second.     [At 62.500KHz]

So 16 mirco second would taken for one cycle of  conversion.with 62,5KHz.

13 ADC cycles required for one conversion

ie,

    13 * 16Micro Second = 230 Micro Second [approximately]

                                      = 230us.

The Half wave has 10milli second time duration.[100000microsecond].

There the available conversion times is 

                                        =  Total time period for a half cycle /one ADC conversion time  

                                        

                                        = 10000 micro second / 230 micro second

                 

                                        = 43.4 samples  [ for one half cycleie 10 milli second]

                                       

    Image Shows only 7 Samples per half cycles .in our case it is 43

And again reduced the sampling to 40 .

calculation of Vpeak

 Takes the largest Vpeak from the 40 samples.

Vrms = Vpeak * .707

*****************************************************************************

Atmega8 ADC StepSize Calculation

Atmega8 uses successive approximation adc  ,

The Atmega8 ADC is a 10 Bit /[ie the Maximum high value is 1023 =1111111111] at which the ADC will give fullscale Value .

The ADC  require a clock as well as a reference voltage .

The resolution of ADC output decide the Step size.

ADC o/p = Vin * 1024 / Vref

Examples;

  Vin =5volt , Vref =5volt 

                 ADC o/p = 5 * 1023 /5 = 1023 [ADC highest Value]

               Step Size  voltage = Vref / 1023 = 0.004887 volt =4.88millivolt

             One binary digit changes when 4.88volt changes takes place

           

     

Image's Step Size is 1.25 volt

*******************************************************************************************************

Go Here for Part 2 

Read More

Transformer Design Basics

Transformer Design Basics

                          Part 1.

Inverter Transformer ,stepUp transformer ,Step Down Transformer Desgin

            Here trying  provide some basics of transformer design and its tutorials with  series of parts[posts] . Part 1 provide the basics steps.

Design Consideration

1. Power Rating

First we require what rate of transformer we require ,Here we need to decide which rate for example 1000Va ,1500va etc . 

 2.Step Down / Step Up Transformer

Here you should decide what type of transformer you required ,ie Is it step down / Step Up ?

It means that you decide the voltages of primary and secondary.Also decide  the Frequency.

 Eg: Primary -230V Secondary 12V Frequency 50Hz

2.Primary and Secondary Currents

Then You need to select the currents in each windings ie,Primary and Secondary winding.

Eg: if we selct 1000VA then the primary Current 1000/230=4.347.

       The Secondary volt is 12V 

       then Secondary Current is 1000/12 = 83.333  =84Ampere.

2.Primary and Secondary coils wire diameter/size

Next we need to decide the coil diameter .It can be only select from a calculation as each coil has its own capability of current .As shown the table 

2.Iorn Core Area 

Iron Core area is selected in according to how much rating or how much power has been required .

Eg ; if we require 1000VA core Area required 32.cm^2 .[calculation will be provide following          posts]

In according to How much core area we can select corresponding Bobbins .Because each type of Bobbins has their own Core Area . 

Some of Bobbins Table as follows

Details design will be Continue  

 

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Transformer Design Basics

Transformer Design Basics

                          Part 1.

Inverter Transformer ,stepUp transformer ,Step Down Transformer Desgin

            Here trying  provide some basics of transformer design and its tutorials with  series of parts[posts] . Part 1 provide the basics steps.

Design Consideration

1. Power Rating

First we require what rate of transformer we require ,Here we need to decide which rate for example 1000Va ,1500va etc . 

 2.Step Down / Step Up Transformer

Here you should decide what type of transformer you required ,ie Is it step down / Step Up ?

It means that you decide the voltages of primary and secondary.Also decide  the Frequency.

 Eg: Primary -230V Secondary 12V Frequency 50Hz

2.Primary and Secondary Currents

Then You need to select the currents in each windings ie,Primary and Secondary winding.

Eg: if we selct 1000VA then the primary Current 1000/230=4.347.

       The Secondary volt is 12V 

       then Secondary Current is 1000/12 = 83.333  =84Ampere.

2.Primary and Secondary coils wire diameter/size

Next we need to decide the coil diameter .It can be only select from a calculation as each coil has its own capability of current .As shown the table 

2.Iorn Core Area 

Iron Core area is selected in according to how much rating or how much power has been required .

Eg ; if we require 1000VA core Area required 32.cm^2 .[calculation will be provide following          posts]

In according to How much core area we can select corresponding Bobbins .Because each type of Bobbins has their own Core Area . 

Some of Bobbins Table as follows

Details design will be Continue  

 

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Development of a DSP-Controlled On-Line UPS

    

This research has developed DSP-based digital control techniques for high-performance single-phase on-line UPS systems. A transformerless common-neutral half-bridge AC-DC-AC converter has been adopted for the main power circuit.  All the control functions for an on-line UPS, which includes power-on start-up control, input stage power factor control, battery charging and boosting control, output stage ac voltage regulation, and shut-down control, were realized by using a single-chip DSP controller, the TMS320F2407A. A multiple rate digital controller generates all the PWM control signals for the power stage by using a set of synchronously detected feedback signals. Software current control scheme with nonlinear pulsewidth compensation has been developed to eliminate the nonlinearity caused by the dead-lock protected PWM converters. A nonlinear digital control scheme with lower switching frequency has been developed for the power factor control of the ac-dc converter. Computer simulation and experimental results have been given to verify the proposed digital control scheme. The constructed DSP-controlled UPS system can achieve fast dynamic response for nonlinear loads and high power factor under various loading conditions. The developed UPS digital control techniques have been applied to a commercialized single-phase 2 kVA double conversion UPS. Excellent performance measurements have been achieved in the designed DSP-controlled UPS. 

        Implementation of a fully digital-controlled UPS provides many advantages, such as more sophisticated control functions can be employed in a UPS system, a software-controlled UPS can be more flexible, advanced robust control schemes can be implemented to accommodate stringent and versatile application requirements. Many research works have been carried out on the closed-loop regulation of PWM inverters using various feedback control schemes to achieve both good dynamic response and low harmonic distortion. Microprocessor-based deadbeat control technique has been applied to the closed-loop regulation of PWM inverters. Deadbeat control has been developed for the voltage regulation of the PWM inverter by employing a minor current loop and a major voltage loop. However, deadbeat control scheme has the disadvantages of highly sensitive to parameter and load variations and requiring large peak-to-average ratio of control signals to achieve deadbeat effect.

With the great advances in microelectronics and VLSI technology, high-performance microprocessor and digital signal processors (DSPs) can be effectively used to realize advanced control schemes [7]. Most instructions of a DSP can be accomplished within one instruction cycle and complicated control algorithms can be executed with fast speed, therefore, more control functions can be realized by using software. Attempts have been made to realize a fully DSP-controlled UPS [8]-[9]. However, only limited functions have been realized using software. In this paper, a single-chip DSP controller, the TMS320F240 from Texas Instruments, has been used to realize all the control functions required in an on-line UPS system. 

        With the availability of 16/32-bit high-performance single-chip DSP, as shown in Fig. 1.3, most of its instructions can be accomplished within one instruction cycle, complicated control algorithms can be realized efficiently. This paper describes the design and implementation of a DSP-embedded fully digital-controlled single-phase on-line uninterruptible power supply (UPS) system. All the control functions for an on-line UPS, which includes power-on start-up control, input stage power factor control, dc-link voltage regulation, battery charging and voltage boosting control, output stage ac voltage regulation, and shut-down control, were realized by using a single-chip DSP controller. 

2. Power Circuit Design

        The selection or development of a circuit topology for a single-phase double-conversion UPS plays a most important role in the design of a high-performance UPS. This is due to that the circuit topology is highly dependent on the overall efficiency, cost, safety regulations, and possible patent conflicts

 2.1 Half-Bridge Common-Neutral AC-DC-AC Converter

        Single-ended, half-bridge, or full-bridge PFC converters are all boost converters, from the point-of-view of control loop design they have the same dynamics. The only difference is the effective voltage applied to the inductor due to a specified PWM duty. From the point-of-view of power circuit design, these three PFC converters have the same utilization factor, which result the processing power ratings are proportional to their number of switches. The half-bridge PFC converter has advantages of common-neutral in UPS applications and a minimal number of power switches is required. However, it also has disadvantages of higher voltage stress and need fast response balance control of the totem-pole capacitor bank. Fig. 2.2 shows the detailed schematics of the power circuit of the common-neutral ac-dc-ac converter and Fig. 2.3 is an illustrated circuit topology for functional description and component rating calculations.  

Figure 2.3  Common-neutral half-bridge ac-dc-ac converter.

Figure 2.2  Schematics of the Common-neutral half-bridge ac-dc-ac converter.

 The inherent bi-directional characteristics of a common-neutral ac-dc-ac converter can be illustrated as shown in Fig. 2.4. The UPS output connected load may be inductive, capacitive, or even nonlinear with reactive characteristics, therefore, in order to a unit power factor input as well as keep a good dynamic response under step load change condition, the dc-link capacitor should provide a sufficient energy storage to maintain a half-cycle voltage fluctuation.

 2.2 PFC Converter 

        Single-ended, half-bridge, or full-bridge PFC converters are all boost converters, from the point-of-view of control loop design they have the same dynamics. The only difference is the effective voltage applied to the inductor due to a specified PWM duty. From the point-of-view of power circuit design, these three PFC converters have the same utilization factor, which result the processing power ratings are proportional to their number of switches. The half-bridge PFC converter has advantages of common-neutral in UPS applications and a minimal number of power switches is required. However, it also has disadvantages of higher voltage stress and need fast response balance control of the totem-pole capacitor bank.   

3. Control Loop Design

        There are many control functions required in a smart UPS system, These may include system monitoring, diagnosis, protection, interface control, and real-time control. The real-time control function plays an important role for the improvement of the UPS control performance. The control functions of a UPS system can be classified four major parts according to their control purposes. These include: front-end power factor correction control, PWM inverter control for sinusoidal output voltage regulation, the dc-dc boost control for dc-link voltage regulation, and the battery charging control. These control functions are described as follows. 

3.1 Power Factor Control 

        Regulations on line current harmonics have made power factor control a basic requirement for power electronic equipment [14]. The main purpose of the PFC converter is to shape the input current to be linear proportional to its input voltage so that it behaves as a resistor. Another purpose of the PFC converter is to regulate its output dc voltage under line and load variations. 

        Conventional PFC control schemes focus on the shaping of the line current in proportional to the voltage and therefore, a current loop controller with wide bandwidth is required. However, in order to minimize the current distortion resulted from the dc-link voltage regulation, a low-pass filter is required to smooth the double line frequency ripples in the dc-link voltage. This results a slow response of the UPS front-stage power converter. The slow response of the PFC converter will result a large voltage drop under a step load change and further deteriorate the UPS output waveform. 

        In order to improve the dynamic response of the PFC boost converter, various feedback control schemes have been analyzed in [15]. Analog notch filter to eliminate measured output voltage ripples can achieve a better dynamic response compared with other approaches. Development of fast response control schemes for the PFC boost converter has become a technical pursuing goal in recent years [16]-[19]. These control techniques break the bandwidth barrier of double line frequency by using sophisticated control techniques in elimination the influences of output voltage ripples. All these control schemes are applied to the PFC boost converter and using analog controller or analog current-loop controller with microprocessor-based voltage-loop controller.

        One major design challenge in synthesizing a digital PFC controller is that we must make a compromise between the line current distortion and a fast response of the dc-link voltage regulation. Fig. 3.1 shows the control structure of a single-phase PFC converter and Fig. 3.2 is the detailed control block diagram. The PFC controller consists of three sub-controllers: an inner current loop controller, an outer voltage loop controller, and an adaptive ripple estimator.

    The inner current loop controller is required to regulate the line current with a high sampling rate, usually from 10 to 20 kHz. The outer voltage loop controller is used to regulate the dc-link voltage and at the same time to generate a current reference for the current loop. A lower sampling rate from 1 to 2 kHz is an appropriate choice for the voltage loop. The adaptive voltage ripple estimator is used to generate a compensated signal to cancel the line ripple voltage occurred in the dc-link. 

                    Figure 3.1  Control structure of a single-phase PFC converter.

Figure 3.2  Detailed control block diagram of a digital-controlled half-bridge PFC converter.

3.2 PWM Inverter Control 

        The control loop design for the PWM inverter for ac voltage regulation is most difficult in the synthesis of the digital controller for the UPS. This is due to that the inverter should provide good quality ac voltage, this means low voltage THD, for various kinds of loads. The control architecture of the PWM inverter for ac voltage regulation is shown in Fig. 3.3. It includs four control loops.

1. Balancing Control Loop (fs=60 Hz): This loop is used to compensate dc-offset due to nonlinear distortion such as unbalanced turn-on and turn-off time, unbalance of the upper and lower common-neutral dc-link voltages, and possible dc-offsets of the feedback sensing circuits. 
2. RMS Control Loop (fs=60 Hz): This loop is used to compensate RMS voltage errors due to limited voltage loop bandwidth and output voltage THD distortion when connected with nonlinear loads. 
3. Voltage Control Loop (fs=6 kHz): This loop is used to compensate the instantaneous output voltage to track a sinusoidal 60 Hz reference. The desired closed-loop bandwidth (600 Hz) should be at least ten times of the reference frequency (60 Hz). A 10 times of sampling frequency to BW ratio means the voltage loop sampling frequency should be 6 kHz. 
4. Current Control Loop (fs=24 kHz): The current loop plays a most important role in the control of a PWM inverter for ac voltage regulation. This loop can decouple the inductor from the LC filter dynamics and eliminate nonlinear distortion due to dead-time of the PWM inverter. 
5. 
   Figure 3.3  Control architecture of the PWM inverter for ac voltage regulation.
6. The current loop controller can decouple the nonlinear dynamics resulted by the load. The dynamics of the UPS inverter output filter with its connected load exhibits large load variations. Fig. 3.4 shows the frequency responses of the inverter with resistor load (10% ~100% load). It can be observed that the frequency response exhibits highly resonant characteristics at resonant frequency of the output filter when in light load. In order to achieve good dynamics responses and maintain good stability under large nonlinear load variation conditions, an adaptive variable structure control scheme, as shown in Fig. 3.5,  has been developed for the PWM inverter for robust ac voltage regulation. 
7. 
   
   
   
   Figure 3.5  Block diagram of the digital adaptive variable structure control scheme for AC voltage regulation.

8. 3.3 DC-DC Booster Control 

           The booster in a UPS system is used to convert the battery output voltage to a much more high dc-link voltage. The battery booster in the designed UPS system is a common-neutral current-fed flyback converter with a coupled transformer. The PI control scheme has been applied for the inner current loop control of the boost converter. Because the booster output is connected to the dc-link and is activated when the utility is failed, its dynamic response behaves as an important performance index. The current-fed flyback converter is current regulated an inner-loop analog PWM controller and voltage regulated by an outer voltage loop controller using PI control with dc-link voltage feedforward compensation. 

   3.4 Battery Charger Control 

           The battery charger in the designed UPS system is symmetric common-neutral flyback converter. A proportional controller is used for the current regulation and a simple PI controller is used for the voltage regulation. Constant current with battery voltage profile control is adopted as the battery charging scheme. The charging profile is stored in the EEPROM of the UPS controller and can be reloaded when a new set of battery are installed. The software control approach provides great flexibility in implementing various intelligent battery charging and discharging control schemes. 

   3.5 Line Frequency Synchronization Control 

           For a double-conversion UPS, its output voltage must always be synchronized with the line voltage. This design requirement is required because in case of UPS failure or manually switched to maintenance mode the UPS output must be transferred to the line input and the synchronization ensures a smooth voltage transfer. If the line frequency is within the specified output frequency range (±3%), the output voltage should synchronize with the input voltage with zero phase error. However, if the line frequency deviation is larger than ±3% for a specified time interval (such as 10 cycles), the frequency of the UPS output voltage will converge to standard output frequency (such as 60 Hz) with a frequency slew rate of 0.1Hz/cycle. If the line frequency back to specified range, the UPS output should also synchronize with the line frequency with a same frequency slew rate. In any instances, the input current should synchronize with the line voltage and provide a proportional current control for input power factor correction.  

   4. UPS Realization 
   
   

   　　Realization of a practical UPS system involves a lot of sophisticated engineering works. In this research we focused on the realization issues of the digital control of the UPS system using a single-chip DSP controller - the TMS320F2407A. 

   4.1 Hardware Architecture  

   　　Fig. 4.1 shows the UPS hardware architecture and the control interface. The UPS consists of two major parts: the power conversion unit and the control unit. In order to unify the control interface for the control of various power converters we have defined a power interface bus, the P-bus, for the control interface between the power converter and the DSP-based control unit. We name UPS control engine for the the DSP-based UPS controller. Fig. 4.2 shows the pin definition of the UPS control engine.  

   
   Figure 4.1  UPS hardware architecture and control interface.
9. 4.2 Selection of the Control Processor
    　　The TMS320Lx240xA series of devices are members of the TMS320 family of digital signal processors (DSPs) designed to meet a wide range of digital motor control (DMC) and other embedded control applications. This series is based on the C2xLP 16-bit, fixed-point, low-power DSP CPU, and is complemented with a wide range of on-chip peripherals and on-chip ROM or flash program memory, plus on-chip dual-access RAM (DARAM). A single-chip DSP controller, the TMS320F2407A, as shown in Fig. 4.3, has been adopted as the control core for the UPS engine. The TMS320F2407A has 32k words on-chip flash memory for program codes. This feature allows program update and flexibility for performance enhancement. 
10. 
    
    Features: 
    • Sectored Flash for field re-programmability and simplified design 
    • Code compatible platform provides easy migration path 
    • CAN module enables inter-system communication 
    • Up to 16 PWM outputs allow multi-motor/axis control 
    • 6.6us to 500-ns A/D converter enhances system accuracy 
    • 33 to 50nS instruction cycle (30 or 20 MIPS) for processing complex control algorithms 
    • RAM for high-level programming language and high-order system modeling 
    • Fast Serial communication Ports 

                      Fast Interrupts Control unit

Figure 4.3  Block diagram and features of a 40MPIS single-chip DSP controller - TMS320F2407A.

4.3 Development of the UPS Control Engine

        The TMS320F2407A running at 40 MHz with a single 3.3V supply voltage, this makes it a challenge in hardware design for electromagnetic interference reduction. Special design considerations must be carried out in the design of the PCBs for the power and control circuits for EMI control. Fig. 4.4 shows the picture of the designed DSP control card for 2U rack-mount UPS systems. This single-board DSP controller is designed to meet high-performance requirement for power electronic systems. 

Special Features:  Control Processor: TMS320F2407A 40 MHz External RAM: 32k Words 8 channels 12-bits D/A conversion  16 channels 10-bits A/D conversion  16 channels for programmed PWM generation  SPI (Serial Peripheral Interface) for multiple-DSP controller  On-board RS-232 and USB interface  FPGA for programmed PWM generation  Figure 4.4  The DSP-based UPS control engine.

4.4 Development of the Power Board 

        Realization of the power board of an on-line UPS system includes a lot of accumulated experienced engineering works, such as  on the components selection, design options for application models, power circuit PCB layout for EMI reduction, and safety requirements, etc.

4.5 System Integration 

        Fig. 4.5 shows the DSP-controlled UPS under development. The developed DSP control techniques have been realized into a commercialized 2kVA UPS to shows the feasibility of employing modern digital control techniques by using an advanced digital signal processor. A systematic top-down design procedure has been developed in the design of the a series of high-performance cost-effective UPS systems for rack-mount server applications.   

4.6 Real-Time Control Firmware Design  

        The control of a power processing system is essential a real-time control problem. Many real-time control tasks can only be tested after the complete hardware has been constructed. It is time consuming for inexperienced engineers in developing these control, communication, and interface software for a commercialized UPS system. Fig. 4.7 shows the system software architecture of an on-line UPS. The control software are classified into three categories: real-time interrupted control routines, periodic background sequential control routines, and aperiodical background interface control routines. Fig. 4.8 illustrate the operating mode and interrupt mechanism of the DSP-based UPS controller and Fig. 4.9 shows the main flow chart of the system software. The interrupt-driven mechanism is activated by a real-time timer. An innovative asynchronous control scheme has been developed for the digital current loop control to achieve both good dynamic response and low electro-magnetic interference (EMI) with low PWM switching frequency.  

6. Conclusions 

　　This research has completed the design and implementation of a DSP-embedded fully digital-controlled single-phase on-line uninterruptible power supply (UPS) system. The applications of high-performance DSP in complicated power electronic systems will find great potential in synthesis of sophisticated control algorithms and PWM switching schemes. This paper has applied a single-chip DSP controller, the TMS320F2407A, in realizing all the required control functions for a single-phase on-line UPS. Experimental results show the designed 2 kVA UPS can reach very good dynamic responses both in utility interface and output voltage regulation.

　　　　Some practical important research issues include: 

• Detection scheme of the PWM switching current under large switching noise condition  
• Sophisticated control functions for ac voltage regulation with low THD and low switching frequency
• Auto-tuning of the control parameters for optimal performance 
• Fast dynamic response of the PFC converter with good power factor 
• Good voltage regulation with nonlinear unbalanced load 
• Achieve AC mode efficiency beyond 92% 
• Reduction of EMI filters by using randomized PWM techniques in PFC converter 
• Optimization of the major power device parameters 

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